1. Field of the Invention
The present invention is related to a communication controlling apparatus, particularly to a communication controlling apparatus capable of back-up when an error has occurred in one of the transmission lines in communication network wherein data are transferred via a transmission lines of two-wire common circuit transmission line.
2. Description of The Related Art
FIG. 1 is a schematic diagram showing a conventional two-wire LAN system and a plurality of nodes connected thereto.
Nodes N1, N2 . . . Nn are connected to a BUS+line 11 and a BUS-line 12 which transmit mutually inverted signals as shown in FIG. 1. The lines 11 and 12 transmit and receive the message frames to configure a communication system. The message frames complying with a communications protocol must be used in order to configure the two-wire communication system. As an example of such a message frame, FIG. 2 schematically shows the configuration thereof which is designated as "Class B data communication network interface J1850".
A message frame shown in FIG. 2 indicated by reference numeral 9 comprises a code SOF (Start Of Frame) indicated by reference numeral 1 and meaning start of transmission, a priority code 2 which determines the priorities of transmission lines, a destination address 3, a self address 4, a data area 5, an EOD (End Of Data) 6 which is a code indicating the end of transmit data (these are included in a transmission frame 10), an IFR (In Frame Response) area 7 which returns the address of destination node as an acknowledgement when no receive error has occurred at the destination, and an EOF (End Of Frame) 8 which indicates the end of message frame.
FIG. 3 is a schematic diagram showing a pulse width modulated bit pattern defined in a PWM (pulse width modulation) bit format of "Class B data communication network interface J1850" above stated.
A one-bit area for data to be transmitted via the transmission lines comprises three areas which are termed as a Time and each Time has a width of 8 clock cycles.
Bit "0" indicated by reference numeral 100 is expressed by "H" level in both a first Time 63 and a second Time 64, and by "L" level in a third Time 65 as shown in FIG. 3. Bit "1" indicated by reference numeral 101 is expressed by "H" level in the first Time 63, and "L" level in both the second Time 64 and the third Time 65 as shown in FIG. 3.
The code SOF 1 which means the start of transmission is, as shown by reference numeral 102 in FIG. 3, expressed by "H" level in all the first Time 63, the second Time 64, the third Time 65, and a fourth Time 66, and by "L" level in both a fifth Time 67 and a sixth Time 68.
The code EOD 6 which means the end of transmission is, as shown by reference numeral 103 in FIG. 3, expressed by "L" level in all the first Time 63, the second Time 64 and the third Time 65.
The code EOF 8 which means the end of transmission is, as shown by reference numeral 104 in FIG. 3, expressed by "L" level in all the first Time 63 through the sixth Time 68.
Such pulse-width-modulated data is transmitted and received in a message frame format such as, for example, SAE J1850 shown in FIG. 2. When sending the transmit frame 10, the SOF 1 is transmitted and then the priority code 2, destination address 3, self address 4, data area 5 which is the PWM data comprising a bit. "0" or "1", and EOD 6 meaning the end of transmission of data area 5. When no error is detected in receive data, the receive side returns a peculiar address that is allocated to itself as the IFR area 7 after PWM modulation. Then, the EOF 8 meaning the end of one message frame is transmitted; that is, the transmission of the message frame 9 terminates.
The transmit circuit and receive circuit of the conventional communication controlling apparatus are described referring to FIG. 4.
In FIG. 4, reference numerals 11 and 12 indicate the BUS+line and BUS-line, respectively shown in FIG. 1, and a plurality of nodes of the same configuration indicated by reference symbol N are connected to these lines 11 and 12.
Reference numeral 16 indicates a transmit buffer memory in which data to be transmitted. The transmission buffer memory 16 stores each data of the priority code 2, destination address 3, self address 4 and data area 5 comprising the transmit frame 10 shown in FIG. 2.
Data stored in the transmit buffer memory 16 is, before transmissions composed into the transmit frame 10 shown in FIG. 2 by a transmit frame composing circuit 17 described later. No-conversion data of the transmit frame 10 is transmitted to the BUS+line 11 via a NAND gate indicated by reference numeral 18 and P-channel MOS transistor indicated by reference numeral 20; and inversion data transmitted to the BUS-line 12, being inverted, via an AND gate indicated by reference numeral 19 and an N-channel MOS transistor indicated by reference numeral 21. That is, transmit data is in opposite polarities in the BUS+line 11 and BUS-line 12 to each other.
In the P-channel MOS transistor 20, its source is connected to a voltage VDD of the power supply 22, its gate is connected to the output terminal of the NAND gate 18, and its drain is connected to the BUS+line 11 as well as grounded via a pull-down resistance 34. In the N-channel MOS transistor 21, its source is connected to a ground voltage GND, its gate is connected to the output terminal of the AND gate 19, and its drain is connected to the BUS-line 12 as well as to a voltage VDD of a power supply 22 via a pull-up resistance 35.
The reason why the drains of the P-channel MOS transistor 20 and N-channel MOS transistor 21 are used as outputs is to detect the collisions of communications by the priority code 2 which determines the exclusive right of transmission lines as described above. That is, when several nodes simultaneously start transmission, the waveform of one of the transmission nodes, which turns on the transistors 20 and 21 for a longer time, appears on the transmission line, and thus the transmission node gains the right to use the transmission line. Such priority control is not the subject of the present invention, and so further explanation is omitted.
Data waveform in the transmission line is inputted to the differential comparators indicated by reference numerals 24, 25 and 26 when it is received.
The BUS+line 11 is connected to the + side input terminal of the first differential comparator 24 and the BUS-line 12 is connected to the - side input terminal of the same. The BUS+line 11 is connected to the + side input terminal of the second differential comparator 25 and the BUS-line 12 is connected to the + side input terminal of the third differential comparator 26; and the - input terminals of the differential comparators 25 and 26 are connected to the voltage VDD/2 which is a half reference voltage supplied by a reference power supply 23. The outputs of these differential comparators 24, 25 and 26 are inputted to a selector 27.
The selector 27 usually outputs the output of the first differential comparator 24 to a receive frame decoding circuit 28. The receive frame decoding circuit 28 demodulates the received data and detects receive errors, and stores it in a receive buffer memory 29.
In FIG. 4, a transmission line error detecting circuit indicated by reference numeral 30 is connected to the BUS+line 11 and BUS-line 12, and it detects an error when either one of the line 11 or 12 is not operating. It determines the errors by various conditions; but it is not explained here because it is not the subject of the present invention.
When the transmission line error detecting circuit 30 detects an error in either line 11 or 12, one of the NAND gate 18 or AND gate 19 for driving the line 11 or 12 in which an error is detected respectively, is disabled. Concretely, transmission line error detecting circuit 30 disables and protects the P-channel MOS transistor 20 by setting a signal 18a inputted to the NAND gate 18 to the "L" level, and disables and protects the N-channel MOS transistor 21 by setting a signal 19a inputted to the AND gate 19 to the "L" level. At the same time, the selector 27 selects the second differential comparator 25 or third differential comparator 26 connected to the BUS+line 11 or BUS-line 12, respectively, wherein an error is not detected; whereby communications are switched to one of the above two lines with no error detected.
Problems in the prior art abovementioned are described referring to schematic diagrams in FIG. 5, FIG. 6 and FIG. 7 which show the state where troubles are generated in the schematic diagram in FIG. 1.
FIG. 5 shows the state where the BUS+line 11 is grounded because a trouble indicated by reference numeral 36 has occurred.
FIG. 6 shows the state where the BUS+line 11 is connected to the power supply because a trouble indicated by reference numeral 37 has occurred.
In the examples shown in FIG. 5 and FIG. 6, all the nodes N1, N2, N3 . . . detect errors on the BUS+line 11; therefore they disconnect the BUS+line 11 and switch to one-wire communication done only by the BUS-line 12.
FIG. 7 shows a state where a trouble indicated by reference numeral 38 has occurred in the first node N1 and the signal line connecting it to the BUS-line 12 is disconnected.
In the state shown in FIG. 7, the first node N1 detects an error in the BUS-line 12 from the state of the transmission line and so separates it and switches to one-wire communication done by the BUS+line 11. At this moment, the other nodes N2, N3 . . . have not detected the error. However, the first node N1 has switched to one-wire communication done by the BUS+line 11; therefore in the case where the first node N1 performs transmission to the other nodes N2, N3 . . . , only the BUS+line 11 is driven. Consequently, although the nodes N2, N3 . . . other than the first node N1 are normal themselves, they detect an error on the BUS-line 12. As the result, other than the first node N1, the nodes N2, N3 . . . switch to one-wire communication done-by the BUS+line 11; thus the entire system switches to one-wire communications state.
The problems of the prior art are described by referring to the schematic diagrams in FIG. 8 and FIG. 9.
In the conventional two-wire common circuit, when one of the two lines is defective, communication is secured by continuing transmitting and receiving by the other line which is not defective. This function (state) is termed one-wire backup function (state). However, in this state, there are following problems when compared with the state where two wires are normally operating.
FIG. 8 is a waveform diagram to explain an operation of the first differential comparator 24 shown in FIG. 4, and FIG. 9 is a waveform diagram to explain an operation of the second differential comparator 25 shown in the same. When two wires are normally operating, the signals received from the first differential comparator 24 are selected; when the BUS+line 11 is normally operating and the BUS-line 12 is not, the signals received from the second differential comparator 25 are selected. When the BUS-line 12 is normally operating and the BUS+line 11 is not, the signals received from the third differential comparator 26 are selected.
An output voltage V24 of the first differential comparator 24 whereto two signals from the BUS+line 11 and BUS-line 12 are inputted goes high ("H" level) when the voltage V11 of the BUS+line 11 is higher than the voltage V12 of the BUS-line 12 and goes low ("L" level) when the former is lower than the latter as shown in FIG. 8.
An output voltage V25 of the second differential comparator 25 whereto the signals from the BUS+line 11 and a voltage V23 (VDD/2) of the reference power supply 23 are inputted goes high ("H" level) when a voltage V11 of the BUS+line 11 is higher than the reference voltage V23 (VDD/2) and goes low ("L" level) when the former is lower than the latter as shown in FIG. 9.
The P-channel MOS transistor 20 and N-channel MOS transistor 21 driving the BUS+line 11 and BUS-line 12 respectively, are open drain output. Consequently, the rising delay at the time when the BUS+line 11 is changed from the "L" level to the "H" level is determined by the driving current of the P-channel MOS transistor 20. When the BUS+line 11 changes from the "H" level to the "L" level, its falling delay is determined by the stray capacitance of the transmission line and a pull-down resistance 34 regardless of the P-channel MOS transistor 20.
The same phenomena as shown in FIG. 9 are found in the BUS-line 12 connected to the third differential comparator 26 with only one difference in polarity.
When the stray capacitance of the BUS+line 11 is greater than that of the BUS-line 12, the time required for changing of the BUS+line 11 to "L" level from "H" level is longer than that required for changing of the BUS-line 12 to "H" level from "L" level as shown in FIG. 8. The rising delay and falling delay of a waveform of an output signal 241 of the first differential comparator 24 are assumed to be 40a and 41a, respectively, as shown in FIG. 8. The rising delay and falling delay of a waveform of an output signal 251 of the second differential comparator 25 are assumed to be 40b and 41b, respectively, as shown in FIG. 9.
In this case, concerning the rising delays 40a and 40b, the effect of stray capacitance can be made smaller by boosting up the current driving capabilities of the MOS transistors 20 and 21. However, the falling delays 41a and 41b are influenced by the stray capacitance and the time for the falling delay of the BUS+line 11 becomes long as shown in FIG. 8 and FIG. 9. When looking at the waveforms of the output signals 241 and 251 of the first differential comparator 24 and second differential comparator 25, respectively, the rising delay 41a of the former is shorter than the falling delay 41b of the latter. This is caused by that the voltage V23 of the reference power supply 23 for the second differential comparator 25 is fixed to VDD/2.
As described above, since the output of the second differential comparator 25 or third differential comparator 26 is selected, their rising and falling delays are influenced by the stray capacitance of transmission lines when the system is in the one-wire backup state in the communications networks where data is transmitted and received via the conventional two-wire common circuit transmission lines. The higher data transfer speed is, the greater problem of the delays is. Consequently, it is required that one-wire communication be avoided as much as possible in the two-wire common circuit.